MIPS Partnered With Xcelsa for Chip Optimization
The collaboration leverages autonomous compute intelligence to reduce silicon timing-path delays.
Updated on Sept. 30, 2026 in Semiconductors
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MIPS, a subsidiary of GlobalFoundries, has entered a non-exclusive partnership with Xcelsa Labs to integrate the Apex Design Optimisation platform. The technology aims to accelerate custom silicon development by moving beyond traditional design automation tools.
Why it matters
The shift responds to increasing demand for custom silicon that aligns with specific software and workload requirements within tighter product schedules. By automating critical-path adjustments, the collaboration seeks to eliminate bottlenecks that typically stall chip development.
The Apex Design Optimisation platform reduced critical-path delay by 33 percent while closing a timing-violating path in under three hours. A manual workflow for the same task typically requires one month of engineering time.
The players
MIPS
A subsidiary of GlobalFoundries that designs processor architectures and intellectual property for high-performance computing.
Xcelsa Labs
A technology developer focused on verified compute intelligence platforms for chip architecture optimization.
The details
MIPS deployed the platform to explore design alternatives using physical and verified compute intelligence. This approach allows the system to optimize power, performance, and area without relying on standard electronic design automation (EDA) software—the traditional tools used to design and verify integrated circuits. By iterating at AI speeds, the system autonomously identifies and corrects timing violations that would otherwise require manual intervention by engineers.
Timeline
September 30, 2026: MIPS announced the partnership with Xcelsa Labs.
The Tech Race
This integration challenges the reliance on legacy electronic design automation tools that currently dominate the chip design lifecycle. It shifts the competitive landscape by automating processes that have historically served as the primary bottleneck for custom silicon production.
The platform enables hardware teams to move through the design-validation loop significantly faster than current manual methods allow. This change primarily affects silicon engineers and system architects working on custom processors by potentially reducing the time-to-market for complex workloads.
The takeaway
This partnership signals a transition toward autonomous, AI-driven chip design to meet the scaling demands of modern software. Readers should watch for future reports on the platform's performance when applied to full-scale SoCs (systems on a chip) to confirm these performance gains.
Further reading
For broader trends in silicon design efficiency, visit the Semiconductors section.
Source note: This article includes information reported by Electronicsb2b.
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