Arteris Released FlexGen Multi-Die Chiplet IP
The network-on-chip IP uses virtual channels to optimize I/O utilization for AI and high-performance computing chiplets.
Updated on Sept. 22, 2026 in Semiconductors
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Arteris has released its FlexGen Multi-Die network-on-chip IP product, designed to improve connectivity across chiplet-based architectures. The technology is currently available to early-access partners and strategic customers.
Why it matters
Multi-die integration remains a core challenge in semiconductor design as developers seek to scale performance. This IP aims to reduce the physical footprint and power overhead of die-to-die communication links.
The FlexGen Multi-Die platform supports bidirectional transactions over a single UCIe PHY, achieving a projected 50% reduction in PHY area, power, and I/O requirements compared to conventional designs. It utilizes virtual channel links to manage data flows across physical die boundaries.
The players
Arteris
A provider of system-on-chip interconnect IP and network-on-chip technology for semiconductor design.
The details
The technology functions by extending network-on-chip (NoC) IP—an on-chip communication infrastructure—across die-to-die links. By implementing virtual channels—logical pathways that share a physical link—the product optimizes I/O utilization for non-coherent AI and high-performance computing architectures. The IP integrates with Magillem automation tools and Cycuity hardware security systems to maintain consistent quality of service across the multi-die interface.
Timeline
September 21, 2026: Arteris released the FlexGen Multi-Die product.
The Tech Race
The introduction of FlexGen Multi-Die marks an effort to solve the I/O and power overhead issues inherent in the UCIe standard. It directly competes with internal and third-party interconnect solutions as companies race to scale multi-chiplet AI and high-performance computing systems.
This IP is currently available only to early-access partners and strategic customers building high-performance hardware. Designers working on AI or high-performance computing chiplets can use it to potentially shrink their hardware footprint once they integrate the IP into their own chip flows.
The takeaway
Arteris is betting that managing the physical die boundary through virtual channels is the next frontier for complex chiplet designs. Industry watchers should monitor the release of public benchmarks or deployment reports from early partners to confirm the 50% efficiency claims.
Further reading
For broader context on current interconnect innovations, see our latest coverage in Semiconductors.
Source note: This article includes information reported by eeNews Europe.
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