Sofics Released Specialty I/O for TSMC FinFET Nodes
New interface designs enable 3.3V and 1.8V communication on advanced 4nm and nanosheet manufacturing processes.
Updated on Sept. 25, 2026 in Semiconductors
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Sofics has released specialty input/output (I/O) topologies designed for TSMC FinFET and Nanosheet silicon manufacturing technologies. The IP blocks, which are currently available for licensing, allow high-voltage interfacing on advanced nodes.
Why it matters
These topologies address the technical requirement of connecting advanced, low-voltage processors with sensors and legacy components that operate at higher voltage levels. By integrating the necessary voltage regulation, they simplify system-level design for complex semiconductors.
The 4nm 3.3V general-purpose I/O (GPIO) solution incorporates integrated voltage regulators and ESD protection to safeguard circuitry. This architecture allows designers to tune drive strength, slew rate, and power consumption directly.
The players
Sofics
A provider of specialized I/O and ESD protection intellectual property for semiconductor manufacturers.
TSMC
The world's largest dedicated independent semiconductor foundry, known for its advanced FinFET and Nanosheet manufacturing platforms.
The details
The technology functions by allowing 3.3V signals to interface with systems powered by core supplies, overcoming voltage mismatches in advanced semiconductor fabrication. Sofics utilizes integrated voltage regulators and ESD (electrostatic discharge) protection—a safety mechanism designed to prevent sudden pulses of electricity from damaging chips—within the I/O block to enable compatibility on TSMC FinFET and Nanosheet processes.
Timeline
2010: Sofics joined the TSMC Open Innovation Platform IP Alliance.
September 25, 2026: Sofics announced the availability of its specialty I/O topologies.
The Tech Race
This development aligns with the broader semiconductor industry push to integrate specialized analog functions into highly scaled digital logic nodes. It builds upon Sofics' long-standing integration within the TSMC Open Innovation Platform, which centralizes the ecosystem for third-party design partners.
Hardware engineers and system designers can now license these IP blocks to integrate legacy or sensor-based components into designs using 4nm process technology. The components are available immediately for implementation in new chip architectures.
The takeaway
This release simplifies the integration of mixed-voltage signaling in advanced nodes, which is a major hurdle in system-on-chip design. Engineers should track the integration of these blocks in upcoming 4nm silicon designs to assess the impact on die area and power budget.
Further reading
For more on the current state of advanced chip manufacturing, visit the Semiconductors section.
Source note: This article includes information reported by Design-reuse.
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