Marvell Demonstrated 2nm Optical Interconnects

The company revealed 2nm chip technology designed to scale AI data center bandwidth to 102.4 terabits per second.

Updated on Oct. 2, 2026 in Data Centers

Bold flat-color editorial illustration depicting a semiconductor wafer with optical filaments, symbolizing high-speed data infrastructure. — Marvell Technology has unveiled 2nm optical interconnects capable of 102.4 terabits per second, aiming to address critical power and speed constraints in AI data centers. AI Illustration. Upload story photo >

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Marvell Technology has announced new 2nm optical interconnects, including a co-packaged optics platform capable of 102.4 Tbps total bandwidth. This development, aimed at meeting the increasing power and speed demands of AI infrastructure, remains in the demonstration stage.

Why it matters

Data center operators face critical power constraints as AI model training scales, necessitating more efficient interconnects. This 2nm advancement provides a roadmap to future 3.2T data center architectures by reducing the power required for high-speed data movement.

The platform utilizes 2nm silicon photonics running at 200G per lane, a step up from the 3nm 1.6T Ara platform released in 2024. The demonstration achieves 102.4 Tbps of total throughput, leveraging 800G ZR/ZR+ coherent pluggables for optical connectivity.

The players

Marvell Technology

A semiconductor company specializing in data infrastructure, including high-speed DSPs and silicon photonics for data centers.

The details

Marvell integrates optics directly with switch silicon and AI accelerators using CPO (co-packaged optics) technology, which places optical engines closer to the processing cores to minimize signal degradation. By employing a 2nm process node, the architecture supports 400G-per-lane performance. The system also includes coherent-lite PAM4 (Pulse Amplitude Modulation 4-level, a signaling method that transmits two bits per symbol) and IMDD (Intensity Modulation Direct Detection) to manage signal integrity at these high data rates.

2023: Released 5nm 200G/lane 1.6T Nova DSPs.
2024: Released 3nm 1.6T Ara platform.
September 20-24, 2026: ECOC 2026 conference held in Málaga.
October 2, 2026: Marvell announced 2nm optical interconnect demonstrations.

The Tech Race

This development signals a transition from the 3nm-based 1.6T Ara architecture toward future 3.2T data center interconnects. The move to 2nm silicon photonics reflects an industry-wide race to increase throughput per rack while managing the total power envelope of AI server clusters.

These interconnects are intended for large-scale AI data center operators and will not be available for individual enterprise purchase in the near term. The primary benefit for the broader ecosystem will be a eventual reduction in the power-to-bandwidth cost ratio for cloud-scale AI training.

The takeaway

This announcement confirms the semiconductor industry is aggressively shifting to 2nm nodes to maintain the scaling laws required for next-generation AI accelerators. Watch for the official production volume and energy-efficiency benchmarks of these 2nm DSPs throughout 2027.