Researchers Mapped TSV Residual Stress in Copper
A new study reveals how copper microstructure affects silicon stress in 3-micrometer through-silicon via arrays.
Updated on Sept. 28, 2026 in Semiconductors
Researchers from Purdue University and UCLA have published a study detailing the relationship between copper microstructure and residual stress in silicon.
Why it matters
Understanding stress distribution in TSV architectures is critical for improving the reliability and performance of high-density 3D integrated circuits.
The team analyzed 3-micrometer TSV arrays, observing stress profiles after annealing at 400 degrees Celsius for 60 minutes. The results provide a baseline for material behavior under thermal load.
The players
Purdue University
A public research university known for advanced engineering and semiconductor materials science.
UCLA
A top-tier research institution specializing in nanotechnology and integrated electronic systems.
The details
The researchers employed Raman spectroscopy—a technique using laser light scattering to identify chemical structures and mechanical stress—to image residual stress in silicon at room temperature. To characterize the copper microstructure, they used electron backscatter diffraction, a scanning electron microscope method that determines crystal orientation in polycrystalline materials. By mapping how these microstructures evolve during heat treatment, the team provides insight into how manufacturing thermal cycles induce stress in silicon.
Timeline
September 2026: The research paper was officially published in the journal Advanced Electronic Materials.
The Tech Race
This study addresses a fundamental bottleneck in the transition to more complex 3D chip stacks. It follows a pattern of academic research aimed at resolving thermal instability issues common in current through-silicon via manufacturing processes.
This research provides data that may eventually lead to higher yields and lower failure rates for advanced processors used in high-performance computing. It currently serves as a reference for process engineers working to refine packaging stability in future silicon designs.
The takeaway
The study quantifies how specific copper microstructures react to thermal processing in 3D stacked chips. Industry observers should watch for future design rules incorporating these findings into TSV manufacturing workflows.
Further reading
For more on how materials research influences chip design, visit Semiconductors.
More information
View the complete technical research paper published in Advanced Electronic Materials.
Source note: This article includes information reported by Semiconductor Engineering.
