Researchers Scaled MoS2 Transistors Below 5 Nanometers

The breakthrough demonstrates CMOS-compatible wafer-scale integration for next-generation semiconductor devices.

Updated on Sept. 22, 2026 in Semiconductors

Bold flat-color editorial illustration of a stylized circular semiconductor wafer with a prominent hexagonal lattice, representing advanced transistor research. — Researchers from Carnegie Mellon, MIT, and other institutions have fabricated transistors using molybdenum disulfide with channel lengths below 5 nanometers. AI Illustration. Upload story photo >

Live Poll

Do you believe new semiconductor innovations will make your personal electronic devices significantly better?

Researchers from Carnegie Mellon, University of Florida, MIT, and Texas A&M have developed transistors using monolayer molybdenum disulfide (MoS2) with channel lengths below 5 nanometers. This research-stage development uses a CMOS-compatible fabrication process to achieve 4-inch wafer-scale integration.

Why it matters

This research addresses the physical scaling limits of traditional silicon-based transistors by utilizing 2D materials. Achieving high-performance operation at this scale is critical for continuing the miniaturization trends in high-density integrated circuits.

The transistors achieved an on/off current ratio greater than 10, demonstrating functional switching capabilities at sub-5-nanometer lengths. These results were verified using a 4-inch wafer-scale integration process consistent with established CMOS manufacturing standards.

The players

Carnegie Mellon University

A research university recognized for its advanced work in computer science, engineering, and material fabrication.

Massachusetts Institute of Technology

A private research university with a focus on cutting-edge nanotechnology and semiconductor device architecture.

The details

The team utilized a photolithography-based process, a standard method for pattern transfer in semiconductor manufacturing, to fabricate the monolayer MoS2 transistors. By employing these techniques, the researchers created a CMOS-compatible platform that allows for the integration of 2D material channels onto standard manufacturing substrates. This approach aims to bridge the gap between material-science research and scalable semiconductor device production.

September 2026: The research findings were published in Nature Communications.

The Tech Race

This development marks a significant milestone in the ongoing industry effort to integrate 2D materials into high-density logic architectures. It competes with other research-stage efforts attempting to move beyond silicon by using atomic-layer materials to maintain electrostatic control.

This research-stage breakthrough does not yet affect commercial hardware or consumer devices. It serves as a foundational step that could eventually enable higher-performance, more power-efficient processors for future computing platforms.

The takeaway

The move to sub-5-nanometer architectures using MoS2 demonstrates that scaling limits can be addressed with current manufacturing paradigms. Watch for upcoming industry trials that transition these wafer-scale processes from the lab into commercial pilot lines.