NXP Released MCX A5 Microcontroller With Integrated Ethernet
The new 240-MHz device enables multidrop IP-based networking for industrial applications.
Updated on Sept. 24, 2026 in Semiconductors
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NXP Semiconductors has released the MCX A5, a microcontroller featuring an integrated 10BASE-T1S physical layer (PHY) that supports 25-meter multidrop Ethernet connectivity. This new chip is now available for developers building networked industrial systems.
Why it matters
The integration of Ethernet connectivity directly into a microcontroller reduces the need for external components in industrial field networks. By including post-quantum cryptographic security, NXP aims to future-proof hardware against emerging long-term security threats.
The MCX A5 features a 240-MHz Cortex-M33 core, 2 MB of dual-bank on-chip flash, and dual 16-bit analog-to-digital converters. It supports 25-meter multidrop Ethernet distances, significantly extending the reach of traditional microcontrollers.
The players
NXP Semiconductors
A global semiconductor firm specializing in secure connectivity solutions for embedded applications, industrial automation, and automotive systems.
The details
The device achieves node functionality through an integrated 10BASE-T1S PHY—the hardware component that handles the physical connection to an Ethernet network—allowing for communication across multidrop, or shared-bus, Ethernet topologies. Its security architecture leverages NXP EdgeLock, which includes a hardware root of trust—a secure, immutable foundation for verifying code integrity—and supports post-quantum cryptography to guard against future decryption capabilities.
Timeline
The NXP MCX A5 microcontroller was released on September 24, 2026.
The Tech Race
NXP is positioning the MCX A5 to stay ahead of the transition toward post-quantum security standards defined by the NIST project. This release forces competitors to accelerate the integration of cryptographic hardware to maintain parity in secure industrial networking.
Engineers and industrial system designers can now integrate IP-based Ethernet networks without the overhead of external physical layer components. Developers should evaluate their current hardware stacks to determine if the integrated CAN FD ports and 16-bit ADCs align with existing field-bus requirements.
The takeaway
The move toward integrated PHYs reflects a broader push to simplify the hardware stack for industrial internet-of-things devices. Watch for future development kits that utilize the chip's post-quantum capabilities to establish secure, end-to-end device identity.
Further reading
For broader trends in embedded processing, browse the latest news on Semiconductors.
Source note: This article includes information reported by Electronic Design.
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