Architect Labs Designed AI Chip Using Automated System
The research-stage design process enabled a full hardware redesign in 48 hours to accelerate development.
Updated on Sept. 28, 2026 in Semiconductors
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In August 2026, Architect Labs showcased a research-stage approach to chip design where an AI system generated hardware descriptions and firmware from written specifications. The team successfully produced a bug-free RTL (Register Transfer Level) design and achieved functional validation on an FPGA platform within two weeks.
Why it matters
By automating the hardware description and verification pipeline, the firm aims to collapse the months-long design cycle for custom silicon to better align with the rapid evolution of AI model architectures. This approach could significantly reduce the time required to iterate on specialized inference hardware.
The Redwood chip achieved over 95% functional coverage on FPGA, with the first RTL drop containing zero bugs. The system's performance claims against the Nvidia Jetson Orin Nano are derived from FPGA modeling rather than physical silicon.
The players
Architect Labs
A 25-person startup developing automated hardware design flows for AI inference.
Nvidia
A designer of high-performance GPUs and edge AI hardware platforms like the Jetson series.
The details
The design process centers on an AI agent that manages performance modeling, hardware description, and firmware generation after receiving a written specification. An RTL drop—the logic-level representation of a digital circuit—is then tested on an FPGA, a reconfigurable integrated circuit that acts as a prototype for custom silicon. To implement design changes, the engineers updated the text specification and allowed the AI to regenerate the entire hardware architecture in 48 hours.
Timeline
July 2025: Architect Labs was founded in San Francisco.
June 2026: The company secured $24 million in seed funding.
August 2026: The team published a research paper detailing the automated design process.
The Tech Race
Architect Labs follows the research trajectory established by the DARPA IDEA program, which seeks to automate hardware design processes to lower barriers to entry. The startup aims to outpace the conventional industry design cycle by integrating generative AI into the RTL generation phase.
This research-stage methodology does not yet provide usable consumer hardware, as the Redwood chip has not been manufactured or taped out. The workflow remains a tool for hardware engineers, with future impact contingent on successful silicon fabrication and post-silicon validation.
The takeaway
The firm has demonstrated a proof-of-concept for rapid hardware iteration, but the transition from FPGA prototype to production silicon remains the primary technical hurdle. Observers should track future announcements regarding the company's planned TSMC tapeout and physical silicon validation results.
Further reading
Learn more about the latest developments in chip architecture at Semiconductors.
Source note: This article includes information reported by Startup Fortune.
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